NTUST AIC LAB

Lab介紹

The Subject and Aims of Research

I. Time-to-digital converter: resolution up to 1ps; input range: unlimited; power consumption < 10mW; chip area < 1mm2; FPGA realizable; suitable for high accuracy, low cost and low power systems, such as: laser range finder, high energy particle detection, jitter measurement, missile/defense system.

II. Smart temperature sensor: resolution < 0.1ºC; measurement range > 100º C; error < 0.5º C; power consumption < 1μW; die size << 1mm2; FPGA realizable; suitable for high accuracy, low cost and low power applications, such as: embedded thermal sensor for VLSI chips, FPD thermal compensation, backlight thermal monitoring, environment temperature control.

III. Digital-to-time converter: resolution up to 1.58ps; unlimited output range; FPGA realizable; suitable for low cost IC testing & timing systems, such as: digital pulse generator, data/pattern generator and so on.

IV. Digital pulse width modulator (DPWM): 12-bit high resolution; 97 kHz – 2 MHz wide operation frequency range; 1.249 mW low power consumption at 1 MHz; 0.751 mm2 chip size; small INL of -0.32 – +0.21 LSB at 2MHz; FPGA realizable; suitable for low cost, low power and high accuracy DPWM applications, such as: power management IC, class-D amplifier.

V. On-chip solar cell: conversion efficiency up to 31.47%; high sidewall junction density design; suitable for AIoT self-powered sensors.

High-Efficiency Front-Illuminated On-Chip Solar Cells

Open Circuit Voltage:0.54V

Short Circuit Current:38.17µA

Fill Factor:0.815

Conversion Efficiency:31.47%

VI. Power management IC for solar energy harvesting: conversion efficiency up to 90%; maximum power point tracking; automatic mode switching; startup circuit; suitable for powering AIoT nodes.

Light-Harvesting Interface Based on a Single-Inductor Buck-Boost Converter

Area:1.17mm²

Power Consumption:1.2μW

Peak conversion efficiency:90%@1mW

VII. Low temperature sensitivity resistor less and capacitor less CMOS Relaxation Oscillator: temperature coefficient as low as 5ppm; all-MOSFET oscillator; chip area (2 circuits) < 1mm2; suitable for low cost high performance on-chip oscillator.

Temperature Invariant Resistor-less and capacitor-less Relaxation Oscillator
Area(Two Circuits):0.525mm²
Power Consumption: 108μW

Maximum Oscillation Frequency:1.056MHz

Temperature Coefficient:3.5ppm/ºC

VIII. Ultra-low power voltage reference: power consumption < 100nW, temperature coefficient < 30ppm/ º C; suitable for low cost ultra-low power on-chip voltage reference.

Ultra-Low-Power Voltage Reference Circuit

Area:0.78mm²

Power Consumption:23.9nW

Temperature Range:-20~100ºC

Temperature Coefficient:29.1ppm/ºC

IX. BIST for TDC and DTC: resolution < 10ps; power-on/factory calibration; FPGA realizable; suitable for low cost & high speed TDC/DTC auto-calibration.

X. High accuracy digital-to-analog converter: up to 14-bit resolution with INL< 0.5LSB; current splitting; current steering; SFDR enhancement; suitable for instrumentation.

XI. Ultra-low power wide temperature range analog-to-digital converter: power consumption < 1μ W; operation temperature range > 120º C; suitable for AIoT sensing.

XII. Others: high matching layout research, duty cycle correlator.

High Accuracy 10-Bit Binary-Weighted Current Steering D/A Converter Realized with Enhanced Current Splitter

Area:0.29mm²

Power Consumption:22mW

Sampling Rate:1GHz

INL:+0.48/-0.55LSB       DNL:+0.36/-0.45LSB

SFDR:59.05dB(1.22MHz@1GS/s)


主要研究方向

1. 時間至數位轉換器:解析度已達10ps以下、測量範圍無限、功耗低於10mW、晶片面積小於1mm2,繼續朝5ps解析度目標研發,適用於諸如雷射測距儀、高能粒子量測、時脈抖動量測...等等高精度、低成本、低功耗之系統上。

2. 超低功耗溫度感測器:解析度0.1ºC以下、測量範圍超過100ºC、誤差低於0.5ºC,功耗低於1μW、晶片面積小於1mm2,適用於諸如VLSI晶片之嵌入式感溫器、顯示器溫度補償、背光溫度監控、環境溫度監控...等高精度、低成本、低功耗之應用上。

3. 數位至時間轉換器:解析度3.56 ps、輸出範圍無限、低功耗。

4. 數位脈波寬度調變器:12位元高解析度、97 kHz至2 MHz的寬操作頻率、1.294mW低功率消耗(@1MHz)、晶片面積約為0.751mm2、具-0.32 ~ +0.21LSB之高線性度(@2MHz),適用於低成本、低功耗、高精度DPWM之應用,如電源管理晶片、class-D放大器。

5. 高效率前照式晶片上太陽能電池:最高轉換效率31.47%;高側牆接面密度設計; 適用於自我供電感測器。

6. 應用於光獵能的電源管理晶片:最高轉換效率90%、MPPT、自動模式切換

7. 具低溫敏無電阻與電容之弛張振盪器:低溫度係數、全MOSFET振盪器、晶片面積(包含兩組電路)小於1mm2

8. 超低功耗參考電壓源:功耗低於100nW、溫度係數低於30ppm/℃。

9. 其他:高匹配佈局功率、週期校正IC、類比至數位轉換器、數位至類比轉換器。

 

實驗室特色


每人皆有專屬之個人電腦與研究空間,座位寬大舒適。研究設備精良,囊括全配備之Blade 2000工作站、Probe station、時域
反射儀、高頻數位示波器、高精度脈衝產生器、恆溫恆濕箱、電路板雕刻機...等,可達事半功倍之效。

研究論文題目既多且廣,每人皆有不同之題目,畢業前實作過2~3顆IC者,比比皆是。可廣泛學習多種不同之電路設計技巧,範圍涵蓋類比與混合模式IC設計、數位Cell-Based設計,厚植未來職場競爭潛力。

論文與專利同步產出,每人皆須接受論文研讀、IC研發、IC測試、論文撰寫與專利申請文寫作之完整訓練,大幅提升畢業後之職場競爭力。採研究生自主式管理,學長姊與學弟妹間相處融,學習風氣鼎盛,研究經驗傳承快速。每星期皆須meeting,報告研讀論文精華、研究成果或所遭遇之困難,大幅縮短研究時程。

 



未來出路



LCD IC設計與應用:
凌陽、矽創、聯詠...。

電源 IC設計與應用:
崇貿、立琦、德州儀器...。

數位 IC設計與應用:
華邦電子、旺宏、威盛...。

RF IC設計與應用:
華碩、宏達電、華寶、瑞昱...。

國防役就職率百分之百。

 

 

 

 

Analog Integrated Circuit Laboratory

Laboratory Supervisor: Prof. Poki Chen


Energy Harvesting Systems Group

This group focuses in energy harvesting specially for Internet of Things (IoT) devices. Research includes energy harvesting sources and power electronic converters.

 

 

Design of On-Chip Solar Cell for Energy Harvesting

Internet of Things (IoT) enables widespread sensing through the deployment of devices called IoT nodes. IoT nodes should be able to sense, process data, and transmit these data wirelessly. The most practical solution in powering up the IoT node is by harvesting the energy from the ambient sources. Among all of the ambient sources, solar energy harvesting can produce the highest output power. With this, the utilization of on-chip solar cell is needed. By utilizing a CMOS process, higher power can be produced due to its crystalline structure.
A solar cell is basically a PN junction exposed to light. Most of the published materials utilized the bottom-plate junction. However, light needs to penetrate the material to reach the PN junction, specially if the solar cell is constructed from low doping concentration layers such as the P-substrate and N-well. To solve this problem, sidewall junctions were instead utilized to expose the PN junction to the surface. The main goal for this research is to design the most efficient on-chip solar cell by optimizing its layout. Layout parameters, such as the metal line width, metal line distance, N-well width, etc., are varied and optimized to increase the sidewalls exposed in the surface per unit area. The current design exhibits a conversion efficiency of about 31.47% which is relatively higher compared to the efficiency of any existing on-chip solar cell design.

 

 

Design of Series-Connected On-Chip Solar Cells

Typically, a single solar cell can provide a maximum voltage (open-circuit voltage) of about 0.5 to 0.6 volts, which is not enough to power a circuit. One way of voltage boosting is by utilizing a DC to DC converter. This method is commonly used due to its main advantage: high conversion efficiency. However, this may not be applicable in some applications due to its utilization of bulky elements such as inductor. For instance, in IoT smart dust applications, where each smart dust is only 1 mm × 1 mm × 1mm in dimension, it is not advisable to use a DC to DC converter-based voltage booster. For applications that requires smaller area, A series connection of solar cell is more realizable.
Published materials had shown poor performance for such series connection method. The main problem in fabricating solar cells in a standard CMOS process is the common P-type substrate, thus the anode of both solar cells is not electrically isolated. By introducing the Deep N-Well layer, electrical isolation between the anodes can be achieved. To further increase the performance, low doping concentration layers, such as P-substrate, N-Well, Deep N-Well, and P-Well, are used. To produce the best efficiency, layout optimization for the two solar cells were done. Design parameters for each cell includes metal line width, metal line distance, well width, etc. Also, area ratio between the two cells are optimized to further improve the overall performance of the series-connected solar cells.


 

 

Design of Power Management Unit for Solar Energy Harvesting

In our application, the power management plays an important role in the entire system. Due to the use of solar energy as our input source, the power management unit must allow the overall system (for example, an IoT node) to operate in different conditions. For example, the output
voltage must be stable under sunny or cloudy conditions. To solve these problems, the architecture of our PMU contains a mode controller, a hysteresis comparator, an adaptive on-time (AOT) controller, a current-sensing circuit, a zero-current detection circuit, a non-overlapping circuit, a driving circuit, and a bandgap reference circuit. In order to ensure that the harvested solar energy of the source stays at the maximum power point, a maximum power point tracking (MPPT) circuit is also used in the system.

The proposed converter features four different operating modes, namely, harvesting, recycling, storing, and auxiliary mode. The operating mode is automatically selected according to the input and load conditions using the automatic selection mode.
After post-simulation, the proposed power management unit’s conversion efficiency reached 93%, and the maximum power point tracking efficiency reached 99%.

Ultra-Low Power Analog Systems Group

This group focuses on the design of ultra-low power analog circuits. Research includes ultra-low power sensors, and ultra-low power data conversion circuits.


Design of Ultra-Low Power Temperature-to-Digital Converter (TDC)

Minimal circuit and power consumption have become a key design requirement for the Internet of Things (IoT), mobile devices, green consumption, and smart applications. The traditional smart temperature sensor converts the temperature into a voltage or current signal through an analog temperature sensor, and then uses an Analog-to-Digital Converter (ADC) to convert the signal into a digital output. However, the high-precision ADC is not only difficult to design but also requires more cost, area, and power consumption. Therefore, time-domain smart temperature sensors will replace traditional smart temperature sensors in the future.

A fully integrated CMOS temperature-to-digital converter (TDC) utilizing MOSFETs in the sub-threshold region is proposed for battery-operated and ultra-low power microsystems. The proposed TDC structure is using a time-domain counter-based. The sensor is implemented in 0.18 μm CMOS with a supply voltage of 600mV. With a conversion time of 20 ms, 0.08°C (rms) resolution is achieved. The power consumption is less than 75nW with an inaccuracy of +0.86°C/-0.71°C from -20°C to 80°C. The sensor does not require any external references and consumes only 1.5 nJ per conversion.


Design of 12-bit Ultra-Low Power Analog-to-Digital Converter

In recent years, with the rapid development of the semiconductor and network industry, Internet of Things has appeared in many applications, especially in the traces of temperature sensors. For example, in the application of forest disaster prevention and crop growth environment monitoring, there is a need for a temperature sensor system that can operate independently in the field without socket power supply, so the laboratory is developing a self-powered intelligent temperature sensing system. This research describes the design of the circuits in this system, namely ultra-low power 12-bit analog to digital converter (ADC) with the low-dropout regulator that can provide a stable power supply for analog-to-digital converters.

The design is fabricated in a TSMC 0.18μm 1P6M CMOS process with a wafer area of 1.04mm2 containing PADs. The core circuit area is about 0.204𝑚𝑚2 (461.28𝜇𝑚 × 442.66𝜇𝑚). The resolution of the SAR ADC is 12 bits, the sampling rate is 1k-Samples/s, and the supply voltage is 0.5V. The power consumption of the post-layout simulation at room temperature is 4.05nW, the effective number of bits after voting modes is enabled is 10.7-bit and the FOM is 2.42 fJ/c-s.

Time-Domain Systems Group

This group focuses on FPGA-based time-domain data converters. Research includes high resolution and high linearity design of both time-to-digital and digital-to-time converters.


FPGA Based Time-to-Digital Converter Design

An extremely high-resolution two-dimensional Vernier FPGA time-to-digital converter (TDC) with phase wrapping and averaging was proposed to get an extremely fine resolution of 2.5ps recently. However, the cell delays in delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays and the input range is limited to be less than 20ns. To achieve both high precision phase division and wide measurement range, a phase-locked loop (PLL) based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this paper. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL) and RMS resolution are measured to be merely -0.157 to 0.137 LSB, -0.176 to 0.184 LSB and 1.0 LSB which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high precision phase division technique can be applied to not only TDC but also digital-to-time converter (DTC) to enrich its future applications.

FPGA Based Digital-to-Time Converter Design

Digital-to-Time Converter (DTC) can also be called Digital Pulse Generator (DPG) or Time Interval Generator (TIG), DTC is a crucial part for modern testing equipment, which main feature is outputting a certain amount of timing delay signal according to the corresponding input control word. In order to reach very high time resolution, DTC design usually using Full-custom design approach, to fine tune the electrical property thus get pico-second level resolution, however, it would introduce lots of design effort and manufacturing cost. In this work, we choose FPGA as our implementation platform due to its flexibility. It is easy to reconfigure DTC design to meet specific application field. There are two design approach for our DTC, one is using PLL Delay Matrix the other is using Fine Phase Shifting feature, both structures provide outstanding timing resolution and stability. Currently we have successfully implemented and evaluated the circuit on both Xilinx Virtex-6 and Altera Stratix-IV platforms, for the Xilinx variant we achieve 14.8ps for time resolution, -0.4~ 0.7 LSB for INL, -0.6~ 0.8 LSB for DNL and 0.3~ 0.9 LSB for STD, on the Altera variant, due to its higher PLL VCO frequency, we achieve 5.2ps for time resolution, -1.8~1.8 LSB for INL, -2.3~ 2.4 LSB for DNL and 0.9~ 1.9 LSB for STD.


 

Analog Circuit Design Group

This group focuses on other analog circuit design which are not mentioned in the previous groups. Research includes relaxation oscillator design, high linearity data converters, LED driver design, etc.


Design of Low Temperature Sensitivity Resistor-less and Capacitor-less CMOS Relaxation Oscillator

It’s a novel design of a self-compensated-temperature relaxation oscillator which does not include any real resistors and real capacitors. This design is being fabricated in standard 0.18μm CMOS process. The overall chip area is 281.65×105.4 μm2 (excluding IO PADs) with a power consumption of 250μW at the typical corner case. This design is capable of producing a temperature coefficient of 33 ppm/°C, over a temperature range from 0 to 140°C with a 1.8V single power supply voltage. Consequently, the post-layout simulation result indicates that new
topology can decrease the effect of process variation and reduce the overall area by nearly one third. Besides, the layout strategy called common centroid generates a second-order gradient error cancellation pattern that improves output frequency performance. This design is suitable as on-chip clock generator for low temperature sensitivity applications.


Design of 10-Bit 1 GS/s Binary-Weighted Current-Steering Digital-to-Analog Converter

A 10-bit 1GS/s digital-to-analog converter realized in a TSMC 90 nm 1P9M CMOS technology with binary-weighted current-steering architecture to achieve high operation speed and high accuracy is proposed. Conventionally, segmented current-steering architecture was usually adopted for high accuracy DAC at the expense of complicated circuitry and high power consumption. To explore the performance limit of binary-weighted structure, a current-splitting architecture along with the second order gradient cancellation layout is adopted to ensure the required accuracy.
The integral non-linearity (INL) and differential non-linearity (DNL) on post-layout simulation are +0.06 LSB ~ -0.06 LSB and +0.08 ~ -0.02 LSB, respectively. With 499.76MHz input sine wave, the spurious free dynamic range (SFDR) is 64 dB. The power consumption is 22mW and the active area is merely 0.29mm2.

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